Serves as a basis for [...] outputs for exactly one cycle. Output x
Ts (end of cycle [...] cycle) wR SMC [...] future (end of cycle
time for a bus task cycle. The planner [...] the bus task cycle
recorded for this cycle [...] . For all trace [...] one timestamp for
_ResetWatchdog CIFX_StartBusCycle CheckFirmwareFor [...] DrvScanModules IoDrvStartBusCycle
milliseconds for one cycle [...] responsible for
outputs for exactly one cycle. Output x [...] description for diagnosis
Comment Input busTaskCycleRef ULINT The cycle of [...] for the planner
state wk, a cycle [...] , an initial cycle [...] -diSign for the
