AXIS_REF_SM3 fCycleTime [...] _REF_SM3 fTaskCycle LREAL [...] AXIS_REF_SM3 fSetActTime

AXIS_REF_SM3 fCycleTime [...] _REF_SM3 fTaskCycle LREAL [...] AXIS_REF_SM3 fSetActTime

AXIS_REF_SM3 fCycleTime [...] _REF_SM3 fTaskCycle LREAL [...] AXIS_REF_SM3 fSetActTime

AXIS_REF_SM3 fCycleTime [...] _REF_SM3 fTaskCycle LREAL [...] AXIS_REF_SM3 fSetActTime

AXIS_REF_SM3 fCycleTime [...] _REF_SM3 fTaskCycle LREAL [...] AXIS_REF_SM3 fSetActTime

AXIS_REF_SM3 fCycleTime [...] _REF_SM3 fTaskCycle LREAL [...] AXIS_REF_SM3 fSetActTime

AXIS_REF_SM3 fCycleTime [...] _REF_SM3 fTaskCycle LREAL [...] AXIS_REF_SM3 fSetActTime

AXIS_REF_SM3 fCycleTime [...] _REF_SM3 fTaskCycle LREAL [...] AXIS_REF_SM3 fSetActTime

time, but signals an [...] in time (udi [...] time and waiting

communication each bus cycle [...] at least one time