DrvWriteOutputs(), and IoDrvStartBusCycle

Sampler (FunctionBlock) Trj_BusTaskCycleInfo (Struct) Trj_BusTaskCycle [...] _DynLimitsAsym_Project (Function) Path_DynLimitsAsym_ProjectJerkEndOfCycle

cycle. ETrigA x [...] : first Ethercat master

less than bus task interval, then the bus [...] cycle at most a

FunCS_IsEq (Function) ElemFunCS_IsInBus [...] FunPose_IsVariable (Function) ElemFunPose_SwitchECSToBusTask (Function) ElemFunPose_SwitchECSToBus

communication each bus cycle

_REF_SM3 fCycle [...] _REF_SM3 fTaskCycle LREAL [...] _REF_SM3 dwBus

_REF_SM3 fCycle [...] _REF_SM3 fTaskCycle LREAL [...] _REF_SM3 dwBus

_REF_SM3 fCycle [...] _REF_SM3 fTaskCycle LREAL [...] _REF_SM3 dwBus

_REF_SM3 fCycle [...] _REF_SM3 fTaskCycle LREAL [...] _REF_SM3 dwBus